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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex Buffers/Logic-Level Down Converters High-Performance Silicon-Gate CMOS The MC54/74HC4049 consists of six inverting buffers, and the MC54/74HC4050 consists of six noninverting buffers. They are identical in pinout to the MC14049UB and MC14050B metal-gate CMOS buffers. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The input protection circuitry on these devices has been modified by eliminating the VCC diodes to allow the use of input voltages up to 15 volts. Thus, the devices may be used as logic-level translators that convert from a high voltage to a low voltage while operating at the low-voltage power supply. They allow MC14000-series CMOS operating up to 15 volts to be interfaced with High-Speed CMOS at 2 to 6 volts. The protection diodes to GND are Zener diodes, which protect the inputs from both positive and negative voltage transients. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 5 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 36 FETs or 9 Equivalent Gates (4049) 24 FETs or 6 Equivalent Gates (4050) MC54/74HC4049 MC54/74HC4050 J SUFFIX CERAMIC PACKAGE CASE 620-10 1 16 16 1 N SUFFIX PLASTIC PACKAGE CASE 648-08 16 1 D SUFFIX SOIC PACKAGE CASE 751B-05 ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXD Ceramic Plastic SOIC PIN ASSIGNMENT LOGIC DIAGRAMS HC4049 (INVERTING BUFFER) A0 2 Y0 VCC Y0 A0 Y1 Y0 A1 Y2 Y1 A2 GND A2 7 6 Y2 A2 7 6 Y2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC Y5 A5 NC Y4 A4 Y3 A3 HC4050 (NONINVERTING BUFFER) A0 3 2 A1 4 Y1 A1 5 4 NC = NO CONNECTION A3 9 10 Y3 A3 9 10 Y3 FUNCTION TABLE A4 11 12 Y4 A4 11 12 Y4 A Input L H Y Outputs HC4049 H L HC4060 L H A5 14 15 Y5 A5 14 15 Y5 PIN 1 = VCC PIN 8 = GND PINS 13, 16 = NO CONNECTION 10/95 (c) Motorola, Inc. 1995 1 REV 6 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I I III I I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Vin = 15 V or GND 6.0 2 20 40 A Iout = 0 A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* MOTOROLA DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) RECOMMENDED OPERATING CONDITIONS MC54/74HC4049 MC54/74HC4050 Symbol Symbol Symbol VCC Vout Tstg ICC Iout VCC Vin Vout PD TL VOH tr, tf Iin VOL Vin ICC TA VIH VIL Iin Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) Storage Temperature Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package DC Supply Current, VCC and GND Pins DC Output Current, per Pin DC Input Current, per Pin DC Output Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Input Rise and Fall Time (Figure 1) Operating Temperature, All Package Types DC Output Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current Maximum Low-Level Output Voltage Minimum High-Level Output Voltage Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter Parameter Parameter Vin = VIH or VIL |Iout| 20 A Vin = VCC or GND Vin = 15 V Vin = VIH or VIL |Iout| |Iout| Vin = VIH or VIL |Iout| |Iout| Vin = VIH |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vout = VCC - 0.1 V |Iout| 20 A v v v v VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Test Conditions - 0.5 to VCC + 0.5 - 65 to + 150 - 0.5 to + 7.0 - 1.5 to + 18 2 - 55 Min 2.0 Value v 4.0 mA v 5.2 mA v 4.0 mA v 5.2 mA 0 0 0 0 0 50 25 20 260 300 750 500 + 125 1000 500 400 VCC to 15 VCC Max 6.0 VCC V 6.0 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Unit Unit mW mA mA mA _C _C _C ns V V V V V V - 55 to 25_C 0.1 0.5 1.5 3.15 4.2 0.26 0.26 3.98 5.48 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the GND pin, only. Extra precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, the ranges GND Vin 15 V and GND Vout VCC are recommended. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Guaranteed Limit v 85_C v 125_C v High-Speed CMOS Logic Data DL129 -- Rev 6 1.0 5.0 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 v v 1.0 5.0 1.5 3.15 4.2 0.40 0.40 3.70 5.20 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 v Unit A V V V V MC54/74HC4049 MC54/74HC4050 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol tPLH, tPHL tTLH, tTHL Cin Parameter VCC V 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C 85 17 14 75 15 13 10 v 85_C v 125_C 105 21 18 95 19 16 10 130 26 22 110 22 19 10 Unit ns Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance ns pF NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Buffer)* 27 pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). tr INPUT A tPHL OUTPUT Y tTHL 90% 50% 10% 90% 50% 10% tf VCC INPUT A GND tPLH OUTPUT Y tTLH tr 90% 50% 10% tPLH 90% 50% 10% tTLH tf VCC GND tPHL tTHL Figure 1a. Switching Waveforms (HC4049) Figure 1b. Switching Waveforms (HC4050) TEST POINT OUTPUT DEVICE UNDER TEST CL* * Includes all probe and jig capacitance Figure 2. Test Circuit High-Speed CMOS Logic Data DL129 -- Rev 6 3 MOTOROLA MC54/74HC4049 MC54/74HC4050 LOGIC DETAIL HC4049 (1/6 of the Device) A Y HC4050 (1/6 of the Device) A Y TYPICAL APPLICATIONS LSTTL to Low-Voltalge HSCMOS 5V IN 3V OUT IN VDD* High-Voltage CMOS to HSCMOS VCC* OUT LSTTL DEVICE HC4049 HC4050 HC DEVICE STANDARD CMOS HC4049 HC4050 HC DEVICE NOTE: To determine the noise immunity for the LSTTL to low-voltage configuration, use Eq. 1 and Eq. 2: (TTL) VOH - (CMOS) VIH Eq. 1 (TTL) VOL - (CMOS) VIL Eq. 2 For the supply levels shown: 2.4 - 3 (75%) = 2.4 - 2.25 = 0.15 V 0.4 - 3 (15%) = 0.4 - 0.45 = 0.05 V Therefore, worst case noise immunity is 50 mV. For supply levels greater than 4.5 volts use the 74HCT04A for direct interface to TTL outputs. MOTOROLA 4 IIIIIIIII I IIIII I IIIIIIIII I IIIIIIIII I IIIII I IIIIIIIII I IIIIIIIII I IIIIIIIII I IIIIIIIII I IIIIIIIII I IIIIIIIII IIIII IIIIIIIII I IIIIIIIII I IIIIIIIII IIIII IIIIIIIII I IIIIIIIII I *Table 1. Supply Examples VDD 15 V 12 V 12 V VCC 2V 5V 3V High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC4049 MC54/74HC4050 OUTLINE DIMENSIONS -A - 16 9 J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V -B - C L 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51 -T SEATING - PLANE N E F G D 16 PL 0.25 (0.010) M K M J 16 PL 0.25 (0.010) M TB S TA S DIM A B C D E F G J K L M N -A - 16 9 N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R B 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01 F S C L -T - H G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M -A - 16 9 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -B - 1 8 P 8 PL 0.25 (0.010) M B M G F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S High-Speed CMOS Logic Data DL129 -- Rev 6 5 MOTOROLA MC54/74HC4049 MC54/74HC4050 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CODELINE 6 *MC54/74HC4049/D* MC54/74HC4049/D High-Speed CMOS Logic Data DL129 -- Rev 6 |
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